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1 zarlink semiconductor inc. zarlink, zl and the zarlink semiconductor logo are trademarks of zarlink semiconductor inc. copyright 2003-2004, zarlink semiconductor inc. all rights reserved. features ? meets jitter requirements of telcordia gr-253- core for oc-48, oc-12, and oc-3 rates ? meets jitter requirements of itu-t g.813 for stm- 16, stm-4 and stm-1 rates ? provides four lvpecl differential output clocks at 77.76 mhz ? provides a cml differential clock programmable to 19.44 mhz, 38.88 mhz, 77.76 mhz and 155.52 mhz ? provides a single-ended cmos clock at 19.44 mhz ? provides enable/disable control of output clocks ? accepts a cmos reference at 19.44 mhz ? 3.3 v supply applications ? sonet/sdh line cards ? network element timing cards description the zl30406 is an analog phase-locked loop (apll) designed to provide rate conversion and jitter attenuation for sdh (synchro nous digital hierarchy) and sonet (synchronous optical network) networking equipment. the zl30406 generates very low jitter clocks that meet the jitter requirements of telcordia gr-253-core oc-48, oc-12, oc-3, oc-1 rates and itu-t g.813 stm-16, stm-4 and stm-1 rates. the zl30406 accepts a cmos compatible reference at 19.44 mhz and generates four lvpecl differential output clocks at 77.76 mhz, a cml differential clock programmable to 19.44 mhz, 38.88 mhz, 77.76 mhz and 155.52 mhz and a single-ended cmos clock at 19.44 mhz. the output clocks can be individually enabled or disabled. june 2004 ordering information ZL30406QGC 64 pin tqfp -40 c to +85 c figure 1 - functional block diagram frequency detector vco c77op/n-a interface circuit lpf fs1-2 c77op/n-b c77op/n-c vdd gnd vcc c77op/n-d c19o c19oen oc-clkop/n oc-clkoen c155o cml-p/n outputs loop filter c77oen-c c19i c77o , c19o, c38o, c77oen-b bias c77oen-a c77oen-d & phase output 19.44mhz 15 reference & bias circuit zl30406 sonet/sdh clock multiplier pll data sheet
zl30406 data sheet 2 zarlink semiconductor inc. figure 2 - tqfp 64 pin (top view) pin description pin description table pin # name description 1gnd ground. 0 volt. 2 vcc1 positive analog power supply. +3.3 v 10% 3vcc positive analog power supply. +3.3 v 10% 4 5 oc-clkon oc-clkop sonet/sdh clock (cml output). these outputs provide a programmable differential cml clock at 19.44 mhz, 38.88 mhz, 77.76 mhz and 155.52 mhz. the output frequency is selected with fs2 and fs1 pins. 6gnd ground. 0 volt 7 vcc2 positive analog power supply. +3.3 v 10% 8 lpf low pass filter (analog). connect to this pin external rc network (r f and c f ) for the low pass filter. 9 gnd ground. 0 volt 10 gnd ground. 0 volt 11 bias bias. see figure 11 for the recommended bias circuit. 50 52 54 56 58 60 62 64 34 36 38 40 44 46 48 42 32 30 28 26 24 22 20 18 gnd vdd gnd vcc vdd vdd gnd gnd nc gnd gnd nc gnd c19o vcc gnd nc c19oen fs1 fs2 ic nc vdd c19i vdd nc nc vdd gnd vcc c77op-c c77on-c gnd vcc c77op-b c77on-b gnd vcc c77op-a c77on-a gnd c77op-d c77on-d vcc 16 14 12 10 6 4 2 8 gnd vcc1 vcc oc-clkon oc-clkop gnd vcc2 lpf c77oen-b c77oen-d gnd bias oc-clkoen c77oen-a c77oen-c gnd gnd gnd gnd gnd zl30406 65 - ep_gnd
zl30406 data sheet 3 zarlink semiconductor inc. 12 oc-clkoen sonet/sdh clock enable (cmos input). if tied high this control pin enables the oc-clkop/n differential driver. pulli ng this input low disables the output clock without deactivati ng differential drivers. 13 c77oen-a c77 clock output enable a (cmos input). if tied high this control pin enables the c77op/n-a output clock. pull ing this input low disables the output clock without deactivati ng differential drivers. 14 c77oen-b c77 clock output enable b (cmos input). if tied high this control pin enables the c77op/n-b output clock. pull ing this input low disables the output clock without deactivati ng differential drivers. 15 c77oen-c c77 clock output enable c (cmos input). if tied high this control pin enables the c77op/n-c output clock. pull ing this input low disables the output clock without deactivati ng differential drivers. 16 c77oen-d c77 clock output enable d (cmos input). if tied high this control pin enables the c77op/n-d output clock. pull ing this input low disables the output clock without deactivati ng differential drivers. 17 gnd ground. 0 volt 18 vdd positive digital power supply. +3.3 v 10% 19 nc no internal bonding connection. leave unconnected. 20 nc no internal bonding connection. leave unconnected. 21 nc no internal bonding connection. leave unconnected. 22 vdd positive digital power supply. +3.3 v 10% 23 ic internal connection. connect this pin to ground (gnd). 24 25 fs2 fs1 frequency select 2-1 (cmos input) . these inputs program the clock frequency on the oc-clko output. th e possible output frequencies are 19.44 mhz (00), 38.88 mhz (01), 77.76 mhz (10), 155.52 mhz (11). 26 c19oen c19o output enable (cmos input). if tied high this control pin enables the c19o output clock. pulling this pin low forces output driver into a high impedance state. 27 gnd ground. 0 volt 28 c19i c19 reference input (cmos input). this pin is a single-ended input reference source used for synchronization. this pin accepts 19.44 mhz. 29 vdd positive digital power supply. +3.3 v 10% 30 gnd ground. 0 volt 31 nc no internal bonding connection. leave unconnected. 32 gnd ground. 0 volt. 33 gnd ground. 0 volt 34 vdd positive digital power supply. +3.3 v 10% 35 c19o c19 clock output (cmos output) . this pin provides a single-ended cmos clock at 19.44 mhz. pin description table (continued) pin # name description
zl30406 data sheet 4 zarlink semiconductor inc. 36 gnd ground. 0 volt 37 nc no internal bonding connection. leave unconnected. 38 gnd ground. 0 volt 39 gnd ground. 0 volt 40 nc no internal bonding connection. leave unconnected. 41 gnd ground. 0 volt 42 vdd positive digital power supply. +3.3 v 10% 43 gnd ground. 0 volt 44 vcc positive analog power supply. +3.3 v 10% 45 gnd ground. 0 volt 46 vdd positive digital power supply. +3.3 v 10% 47 vcc positive analog power supply. +3.3 v 10% 48 gnd ground. 0 volt 49 vcc positive analog power supply. +3.3 v 10%. 50 51 c77on-d c77op-d c77 clock output (lvpecl output) . these outputs provide a differential lvpecl clock at 77.76 mhz. unused lvpe cl port should be left unterminated to decrease supply current. 52 gnd ground. 0 volt 53 vcc positive analog power supply. +3.3 v 10%. 54 55 c77op-c c77on-c c77 clock output (lvpecl output) . these outputs provide a differential lvpecl clock at 77.76 mhz. unused lvpe cl port should be left unterminated to decrease supply current. 56 gnd ground. 0 volt 57 vcc positive analog power supply. +3.3 v 10%. 58 59 c77on-b c77op-b c77 clock output (lvpecl output) . these outputs provide a differential lvpecl clock at 77.76 mhz. unused lvpe cl port should be left unterminated to decrease supply current. 60 gnd ground. 0 volt 61 vcc positive analog power supply. +3.3 v 10%. 62 63 c77op-a c77on-a c77 clock output (lvpecl output) . these outputs provide a differential lvpecl clock at 77.76 mhz. unused lvpe cl port should be left unterminated to decrease supply current. 64 gnd ground. 0 volt 65 ep_gnd exposed die pad ground. 0 volt (connect to gnd) pin description table (continued) pin # name description
zl30406 data sheet 5 zarlink semiconductor inc. 1.0 functional description the zl30406 is an analog phased-locked loop which prov ides rate conversion and jitter attenuation for sonet/sdh oc-48/stm-16, oc-12/stm- 4 and oc-3/stm-1 applications. a functional block diagram of the zl30406 is shown in figure 1 and a brief descri ption is presented in the following sections. 1.1 frequency/phase detector the frequency/phase detector compares the frequency/p hase of the input referenc e signal with the feedback signal from the frequency divider circuit and provides an error signal corresponding to the frequency/phase difference between the two. this error signal is passed to the loop filter circuit and averaged to control the vco frequency. 1.2 loop filter the loop filter is a low pass filter. this low pass filter ensures that the network jitter requirements are met for an input reference frequency of 19.44 mhz. the corner frequency of the loop filter is configurable with an external capacitor and resistor connected to t he lpf pin and ground as shown below. figure 3 - external loop filter 1.3 vco the voltage-controlled oscillator (vco) receives the fi ltered error signal from the loop filter, and based on the voltage of the error signal, generates a primary frequency. the vco output is connected to the output interface circuit that divides vco freq uency and buffers generated clocks. r f c f internal loop filter zl30406 lpf rf=8.2 k ? , cf=470 nf (for 14 khz pll bandwidth)
zl30406 data sheet 6 zarlink semiconductor inc. 1.4 output interface circuit the output of the vco is used by the output interfac e circuit to provide four l vpecl differential clocks at 77.76 mhz, one programmable cml diff erential clock (19.44 mhz, 38.88 mhz , 77.76 mhz, 155.52 mhz) controlled with fs1-2 pins and a single-ended 19.44 mhz output clock. this block prov ides also a 19.44 mhz feedback clock that closes pll loop. each output clock can be enabled or disabled individually with t he associated output enable pin. to reduce power consumption and achieve the lowest possible intrinsic jitter the unused output clocks must be disabled. if any of the lvpecl outp uts are disabled they must be le ft open without any terminations. the output clock frequency of the oc-clk o cml differential output clock is selected with fs1-2 pins as shown in the following table. output clocks output enable pins c77op/n-a c77oen-a c77op/n-b c77oen-b c77op/n-c c77oen-c c77op/n-d c77oen-d oc-clkop/n oc-clkoen c19o c19oen table 1 - output enable control fs2 fs1 oc-clko frequency 0 0 19.44 mhz 0 1 38.88 mhz 1 0 77.76 mhz 1 1 155.52 mhz table 2 - oc-clko clock frequency selection
zl30406 data sheet 7 zarlink semiconductor inc. 2.0 applications 2.1 ultra-low jitter sonet/sdh equipment clocks the zl30406 functionality and performance complements t he entire family of the zarlink?s advanced network synchronization plls. its superior ji tter filtering characteristics exceed requirements of sonet/sdh optical interfaces operating at oc-48/stm-16 rate (2.5 gbit/s). the zl30406 in combination with the mt90401 or the zl30407 (sonet/sdh network element plls) provides the core building blocks for hi gh quality equipment clocks suitable for network synchronization (see figure 4). figure 4 - sonet/sdh equipment timing card mt90401 zl30406 oc-clko cml 38.88 mhz, 19.44 mhz 77.76 mhz 19.44 mhz c77oa lvpecl c77ob lvpecl c77oc lvpecl c77od lvpecl c19o cmos c19i c19o cmos c155o lvds c34o/c44o cmos c16o cmos c8o cmos c6o cmos 19.44 mhz c2o cmos c1.5o cmos f8o cmos f0o cmos 77.76 mhz 77.76 mhz 77.76 mhz 155.52 mhz c4o cmos 34.368 mhz or 44.736 mhz 16.384 mhz 8.192 mhz 6.312 mhz 4.096 mhz 2.048 mhz 1.544 mhz 8 khz 8 khz pri sec prior secor lock holdover refsel refalign r f lpf c f o c - c l k o e n 155.52 mhz, 77.76 mhz c 7 7 o e n - a c 7 7 o e n - b c 7 7 o e n - c c 7 7 o e n - d c 1 9 o e n d s c s r / w a 0 - a 6 d 0 - d 7 up data port controller port synchronization reference clocks note: only main functional connections are shown 20 mhz c 2 0 i f16o cmos ocxo 8 khz or zl30407
zl30406 data sheet 8 zarlink semiconductor inc. the zl30406 in combination with the mt9046 provides an optimum solution for sonet/sdh line cards (see figure 5). figure 5 - sonet/sdh line card mt9046 zl30406 oc-clko cml 38.88 mhz, 19.44 mhz 77.76 mhz 19.44 mhz c77oa lvpecl c77ob lvpecl c77oc lvpecl c77od lvpecl c19o cmos c19i c19o cmos c16o cmos c8o cmos c6o cmos 19.44 mhz c2o cmos c1.5o cmos f8o cmos f0o cmos 77.76 mhz 77.76 mhz 77.76 mhz c4o cmos 16.384 mhz 8.192 mhz 6.312 mhz 4.096 mhz 2.048 mhz 1.544 mhz 8 khz 8 khz pri sec lock holdover rsel r 1 lpf c 1 o c - c l k o e n 155.52 mhz, 77.76 mhz c 7 7 o e n - a c 7 7 o e n - b c 7 7 o e n - c c 7 7 o e n - d c 1 9 o e n m s 1 f s 2 f l o c k uc synchronization reference clocks note: only main functional connections are shown 20 mhz f16o cmos tcxo 8 khz c 2 r 1 = 680 ? c 1 = 820 nf c 2 = 22 nf c20i m s 2 f s 1 p c c i hardware control t c l r
zl30406 data sheet 9 zarlink semiconductor inc. 2.2 recommended interface circuit 2.2.1 lvpecl to lvpecl interface the c77op/n-a, c77op/n-b, c77op/n-b, and c77op/n- d outputs provide differential lvpecl clocks at 77.76 mhz. the lvpecl output drivers require a 50 ? termination connected to the vcc-2v source for each output terminal at the terminating end as shown below. the terminating resistors should be placed as close as possible to the lvpecl receiver. figure 6 - lvpecl to lvpecl interface 2.2.2 cml to cml interface the cmlp/n output provides a differential cml/lvds compatible clock at 19.44 mhz, 38.88 mhz, 77.76 mhz, 155.52 mhz selected with fs1-2 pi ns. the output drivers require a 50 ? load at the terminating end if the receiver is cml type. figure 7 - cml to cml interface lvpecl lvpecl zl30406 z=50 ? z=50 ? c77op-a c77on-a receiver gnd typical resistor values: r1 = 130 ? , r2 =82 ? r1 r2 vcc=+3.3v r1 r2 vcc 0.1uf +3.3v driver zl30406 cml z=50 ? cml 50 ? oc-clkop oc-clkon driver gnd vcc receiver 0.1uf +3.3v 50 ? z=50 ? 0.1uf 0.1uf low impedance dc bias source
zl30406 data sheet 10 zarlink semiconductor inc. 2.2.3 cml to lvds interface to configure the driver as an lvds driver, external biasing resistors are required to set up the common mode voltage as specified by ansi/tia/eia-644 lvds standard. the standard specifies the v cm (common mode voltage) as minimum 1.125 v, typical 1.2 v, and maximum 1.375 v . the following figure provides a recommendation for lvds applications. figure 8 - lvds termination 2.2.4 cml to lvpecl interface in the case when more than four 77.76 mhz clocks are required to dr ive lvpecl receivers then the unused oc- clko clock (cml output) can be configured to output the 77.76mhz clo ck and interface to the lvpecl receiver as is shown in the figure 9. the terminat ing resistors should be placed as clos e as possible to the lvpecl receiver. figure 9 - cml to lvpecl interface zl30406 cml z=50 ? z=50 ? driver 0.1uf +3.3v gnd vcc lvds 10nf 10nf receiver r1 r2 vcc=+3.3v r1 r2 100 ? typical resistor values: r1 = 16k ? , r2 = 10k ? oc-clkop oc-clkon lvpecl cml zl30406 z=50 ? z=50 ? receiver gnd typical resistor values: r1 = 82 ? , r2 =130 ? r1 r2 vcc=+3.3v r1 r2 vcc 0.1uf +3.3v driver 10nf 10nf oc-clkop oc-clkon 77.76mhz
zl30406 data sheet 11 zarlink semiconductor inc. 2.3 tristating lvpecl outputs the zl30406 has four differential 77.76 m hz lvpecl outputs, which can be us ed to drive four different oc-3/oc- 12/oc-48 devices such as framers, mappers and serdes. in the case wher e fewer than four clocks are required, a user can disable unused lvpecl out puts on the zl30406 by pulling the corresponding enable pins low. when disabled, voltage at t he both pins of the differential lvpecl ou tput will be pulled up to vcc - 0.7 v. for applications requiring the lvpecl outputs to be in a tri-state mode, ex ternal ac coupling capacitors can be used as shown in figure 10. typically this mi ght be required in hot swappable applications. resistors r1 and r2 are required for dc bias of the lvpecl driver. capacitors c1 and c2 are used as ac coupling capacitors. during disable mode (c77oen pin pulled low) those capacitors present infinite impedance to the dc signal and to the receiving device this looks like a tristated (high-z) output. resistors r3, r4, r5 and r6 are used to terminate the transmiss ion line with 50 ohm impedance and to generate dc bias voltage for the lvpecl receiver. if the lvpecl receiver has an integrated 50 ohm termination and bias source, resistors r3, r4, r5 and r6 should not be populated. figure 10 - tristatable lvpecl outputs z=50 z=50 c77oen zl30406 0.1u c1 0.1u c2 r4 82.5 r6 82.5 r5 127 r3 127 r1 200 r2 200 3.3v 3.3v
zl30406 data sheet 12 zarlink semiconductor inc. 2.4 power supply and bias circuit filtering recommendations figure 11 presents a complete filtering arrangement that is recommended for applications requiring maximum jitter performance. the level of required f iltering is subject to further optimi zation and simplification. please check zarlink?s web site for updates. figure 11 - power supply and bias circuit filtering 50 52 54 56 58 60 62 64 34 40 44 46 48 42 32 30 28 26 24 22 20 18 gnd vdd gnd vcc vdd vdd gnd gnd gnd gnd vcc vdd vdd vdd gnd vcc gnd vcc gnd vcc gnd vcc 16 14 12 10 6 4 2 8 gnd vcc1 gnd vcc2 gnd gnd gnd gnd gnd gnd 0.1uf 0.1uf 0.1uf 0.1uf 0.1uf ferrite bead 0.1uf 33uf 0.1uf 0.1uf 0.1uf 0.1uf 0.1uf 0.1uf 0.1uf notes: 1. all the ground pins (gnd) and the exposed die pad (metal area at the back of the package) are connected to the same 2. select ferrite bead with i dc > 400ma and r dc in a range from 0.10 ? to 0.15 ? +3.3v power rail zl30406 0.1uf gnd gnd bias 220 ? 11 vcc 0.1uf 36 38 + 0.1uf 4.7 ? 10uf + + 33uf + 33uf 0.1uf 0.1uf
zl30406 data sheet 13 zarlink semiconductor inc. 3.0 characteristics ? voltages are with respect to ground unless otherwise stated. ? exceeding these values may cause permanent damage. functional operation under these conditions is not implied. ? voltages are with respect to ground unless otherwise stated. ? typical figures are for design aid only: not guaranteed and not subject to production testing. ? absolute maximum ratings ? characteristics sym min. ? max. ? units 1 supply voltage v ddr , v ccr tbd tbd v 2 voltage on any pin v pin -0.5 v cc + 0.5 v dd + 0.5 v 3 current on any pin i pin -0.5 30 ma 4 esd rating v esd 1500 v 5 storage temperature t st -55 125 c 6 package power dissipation p pd 1.8 w recommended operating conditions ? characteristics sym. min. typ. ? max. units notes 1 operating temperature t op -40 25 +85 c 2 positive supply v dd , v cc v cc_vco 3.0 3.3 3.6 v dc electrical characteristics ? characteristics sym. min. typ. ? max. units notes 1 supply current i dd +i cc 140 155 ma lvpecl, cml drivers disabled and unterminated 2 incremental supply current to single lvpecl driver (driver enabled and terminated, see figure 6) i lvpecl 40 ma note 1,2 3 incremental supply current to cml driver (driver enabled and terminated, see figure 7) i cml 24 ma note 3 4 cmos: high-level input voltage v ih 0.7v dd v dd v 5 cmos: low-level input voltage v il 00.3v dd v 6 cmos: input leakage current, c19i i il 1uav i = v dd or 0v
zl30406 data sheet 14 zarlink semiconductor inc. ? : voltages are with respect to ground unless otherwise stated. ? :typical figures are for design aid only: not guaranteed and not subject to production testing. note: supply voltage and operating temperature are as per recommended operating conditions note 1: the i lvpecl current is determined by termination network connected to lvpecl outputs. more than 25% of th is current flows outside the chip and it does not contribute to the internal power dissipation. note 2: lvpecl outputs terminated with z t = 50 ? resistors biased to v cc -2v (see figure 6) note 3: cml outputs terminated with z t = 50 ? resistors connected to low impedance dc bias voltage source (see figure 7) 7 cmos: input bias current for pulled-down inputs: fs1, fs2, c77oen-a, c77oen-c, c77oen-d, oc-clkoen i b-pu 300 ua v i = v dd 8 cmos: input bias current for pulled-up inputs: , c77oen-b, c19o_en i b-pd 90 ua v i = 0v 9 cmos: high-level output voltage v oh 2.4 v i oh = 8 ma 10 cmos: low-level output voltage v ol 0.4 v i ol = 4 ma 11 cmos: c19o output rise time (18pf) t r 1.8 3.3 ns 18 pf load 12 cmos: c19o output fall time (18pf) t f 1.1 1.4 ns 18 pf load 13 lvpecl: differential output voltage iv od_lvpecl i 1.30 v note 2 14 lvpecl: offset voltage v os_lvpecl vcc- 1.38 vcc- 1.27 vcc- 1.15 v note 2 15 lvpecl: output rise/fall times t rf 260 ps note 2 16 cml: differential output voltage iv od_cml i 0.70 v note 3 17 cml: offset voltage (also referred to as common mode voltage) v os_cml vcc- 0.58 vcc- 0.54 vcc- 0.50 v note 3 18 cml: output rise/fall times t rf 120 ps note 3 dc electrical characteristics ? (continued) characteristics sym. min. typ. ? max. units notes
zl30406 data sheet 15 zarlink semiconductor inc. figure 12 - output timing parameter measurement voltage levels ? supply voltage and operating temperature are as per recommended operating conditions. ? typical figures are for design aid only: not guaranteed and not subject to production testing. figure 13 - c19i input to c19o and c77o output timing ac electrical ch aracteristics ? - output timing parameters measurement voltage levels characteristics sym cmos ? lvpecl cml units 1 threshold voltage v t-cmos v t-lvpecl v t-cml 0.5v dd 0.5v od_lvpecl 0.5v od_cml v 2 rise and fall threshold voltage high v hm 0.7v dd 0.8v od_lvpecl 0.8v od_cml v 3 rise and fall threshold voltage low v lm 0.3v dd 0.2v od_lvpecl 0.2v od_cml v ac electrical ch aracteristics ? - c19i input to c19o and c77o output timing characteristics sym. min. typ. ? max. units notes 1 c19i to c19o delay t c19d 6.7 ns 2 c19i to c77oa delay t c77d -4 ns v t all signals v hm v lm t if , t of t ir , t or timing reference points c77oa v t-lvpecl c19i v t-cmos (19.44 mhz) t c19d c19o v t-cmos (19.44 mhz) t c77d (77.76 mhz) note: all output clocks have nominal 50% duty cycle.
zl30406 data sheet 16 zarlink semiconductor inc. ac electrical ch aracteristics ? - c19i input to oc-clko output delay timing (cml) ? supply voltage and operating temperature are as per recommended operating conditions. ? typical figures are for design aid only: not guaranteed and not subject to production testing. figure 14 - c19i input to oc-clko output timing characteristics sym. min. typ. ? max. units notes 1 c19i to oc-clko(19) delay t oc-clk19d 3.2 ns 2 c19i to oc-clko(38) delay t oc-clk38d 3.0 ns 3 c19i to oc-clko(77) delay t oc-clk77d 2.7 ns 4 c19i to oc-clko(155) delay t oc-clk155d 2.4 ns oc-clko(38) v t-cml c19i v t-cmos (19.44 mhz) toc-clk19d oc-clko(19) v t-cml (19.44 mhz) toc-clk38d (38.88 mhz) oc-clko(155) v t-cml (155.52 mhz) oc-clko(77) v t-cml (77.76 mhz) toc-clk77d toc-clk155d note: all output clocks have nominal 50% duty cycle.
zl30406 data sheet 17 zarlink semiconductor inc. ? supply voltage and operating temperature are as per recommended operating conditions. ? typical figures are for design aid only: not guaranteed and not subject to production testing. figure 15 - c77ob, c77oc, c77od outputs timing ac electrical characteristics ? - c77 clocks output timing characteristics sym. min. typ. ? max. units notes 1 c77oa to c77ob t c77d-ab 100 ps 2 c77oa to c77oc t c77d-ac 100 ps 3 c77oa to c77od t c77d-ad 100 ps c77od v t-lvpecl c77oc t c77d-ab c77ob c77oa v t-lvpecl v t-lvpecl v t-lvpecl t c77d-ac t c77d-ad note: all output clocks have nominal 50% duty cycle.
zl30406 data sheet 18 zarlink semiconductor inc. performance characteristics - functional- (v cc = 3.3v 10%; t a = -40 to 85 c ) ? typical figures are for design aid only: not guaranteed and not subject to production testing. ? loop filter components: r f =8.2 k ?, c f =470 nf ? typical figures are for design aid only: not guaranteed and not subject to production testing. ? loop filter components: r f =8.2 k ?, c f =470 nf characteristics min. max. units notes 1 pull-in range 1000 ppm 2 lock time 300 ms performance characteristics: output jitter generation - gr-253-core conformance - (v cc = 3.3v 10%; t a = - 40 to 85 c) gr-253-core jitter generation requirements zl30406 jitter generation performance interface (category ii) jitter measurement filter limit in ui equivalent limit in time domain typ. ? max. ? units 1oc-48 sts-48 12 khz - 20 mhz 0.1 uipp 40.2 - 16.9 ps p-p 0.01ui rms 4.02 1.3 2.1 ps rms 2oc-12 sts-12 12 khz - 5 mhz 0.1 uipp 161 - 9.0 ps p-p 0.01ui rms 16.1 0.7 1.3 ps rms performance characteristics: ou tput jitter generation - etsi en 300 462-7-1 conformance - (v cc = 3.3v 10%; t a = -40 to 85 c) en 300 462-7-1 jitter generation requir ements zl30406 jitter generation performance interface jitter measurement filter limit in ui equivalent limit in time domain typ. ? max. ? units 1stm-16 1 mhz to 20 mhz 0.1 uipp 40.2 - 12.6 ps p-p --1.01.5ps rms 5khz to 20mhz 0.5uipp 201 - 17.1 ps p-p --1.32.2ps rms 2stm-4 250khz to 5mhz 0.1 uipp 161 - 5.8 ps p-p - - 0.46 0.9 ps rms 1khz to 5mhz 0.5 uipp 804 - 29.8 ps p-p --2.43.2ps rms
zl30406 data sheet 19 zarlink semiconductor inc. ? typical figures are for design aid only: not guaranteed and not subject to production testing. ? loop filter components: r f =8.2 k ?, c f =470 nf performance characteristics: outp ut jitter generation - g.813 conformance (option 1 and 2) - (v cc = 3.3v 10%; t a = -40 to 85 c) g.813 jitter generation requirement s zl30406 jitter generation performance interface jitter measurement filter limit in ui equivalent limit in time domain typ. ? max. ? units option 1 1stm-16 1 mhz to 20 mhz 0.1 uipp 40.2 - 12.6 ps p-p --1.01.5ps rms 5khz to 20mhz 0.5 uipp 201 - 17.1 ps p-p --1.32.2ps rms 2stm-4 250khz to 5mhz 0.1 uipp 161 - 5.8 ps p-p - - 0.46 0.9 ps rms 1khz to 5mhz 0.5 uipp 804 - 29.8 ps p-p --2.43.2ps rms option 2 3stm-16 12 khz - 20 mhz 0.1 uipp 40.2 - 16.9 ps p-p --1.32.1ps rms 4stm-4 12 khz - 5 mhz 0.1 uipp 161 - 9.0 ps p-p --0.71.3ps rms
c zarlink semiconductor 2002 all rights reserved. apprd. issue date acn package code previous package codes
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